1. Field of the Invention
This invention relates to a method of semiconductor device fabrication, and particularly but not exclusively to a method for fabricating power transistors with a vertical channel MOS gate structure.
2. Description of Related Art
Conventional vertical DMOS power transistors are known having a plurality of xe2x80x98cellsxe2x80x99, each cell comprising a gate disposed on an uppermost surface of a wafer, and a source region located adjacent a lower surface of the gate. A body region is provided beneath the gate and adjacent the source, such that in an on-state a field from the gate forms a horizontal conducting channel in the body, allowing current to flow laterally across the body regions, and through a drain region located between and beneath the body regions to a drain contact located at a lowermost surface of the substrate. Such conventional DMOS structures suffer from the presence of a parasitic Junction-FET region located between adjacent cells, the resistance of which increases rapidly as the spacing between adjacent cells is reduced below a critical dimension. This mechanism creates an inherent packing density limitation, restricting the extent to which on-state resistance in the conventional vertical DMOS structure may be reduced by means of geometry scaling.
The above limitations are mitigated by an alternative known UMOS structure in which the gate regions are disposed adjacent to the vertical sidewalls of U-shaped indentations or trenches formed in a wafer surface. An associated source region is disposed adjacent the upper part of each gate, and a body region is located directly below the source. When the gate region is turned on, a field penetrates from the gate into the body region, thereby forming a vertical conducting channel which allows current to flow vertically between the source and the drain. Because UMOS structures feature such vertical rather than lateral channel regions, they have no parasitic Junction-FET elements and thus do not suffer from the limitations that these elements impose on the conventional DMOS structure.
A method of fabricating a UMOS structure with self-aligned source regions is known from British Patent Specification No. GB 2 264 388. In this known method, a p-type (body) semiconductor region is formed on top of an n-type (drain) semiconductor layer. Practically, the p-type region is likely to be formed either by means of a doped epitaxial deposition of specified thickness onto the surface of the n-type layer, or by the introduction of p-type dopant into the surface of the n-type layer followed by thermal processing to determine the junction depth. A material (typically silicon-dioxide) is grown or deposited on the top surface of this structure and is selectively etched to form a trench masking layer. Trenches or grooves are then formed beneath the apertures in this mask such that they extend from the surface through the p-type region and part-way into the n-type region. A dielectric layer is then formed on the walls of the grooves, and the grooves are partially filled with a gate electrode material, for example polysilicon. This gate electrode material is either deposited at a layer thickness which results in partial filling of the grooves, or (more practically) is initially deposited such that it fills the grooves completely, and then etched back to leave the grooves partially-filled. With the trench-masking layer still in place on the first surface, source dopant is then introduced into the exposed sidewalls of the grooves, above the etched-back gate electrode.
The above known method has advantages with respect to earlier structures (for example that described in FIG. 17 of GB 2 264 388, in which the source dopant is introduced selectively via the substrate surface) because it is not necessary to define via photolithography and with a high degree of accuracy the lateral positional relation between the source regions and the grooves. This allows the distance separating adjacent grooves to be reduced and thereby a higher density of grooves implemented, improving on-state performance. However the method described with reference to FIG. 16 of GB 2 264 388nevertheless still exhibits disadvantages in that the vertical distance separating the source regions from the drain region, known as the channel width, is dependent on the final etched-back position of the top of the gate electrode material. This position is in turn a function of both the initial depth of the grooves, the depth of the initially-deposited gate electrode layer and/or the precise amount of gate electrode material removed during the etchback process step. Variations in these parameters introduce inconsistencies into the channel width dimension, as practically fabricated using this method. It is desirable to minimise the channel width dimension in order to optimise performance when the structure is active, and these inconsistencies restrict the degree to which this can be practically achieved.
It is an object of the present invention to obviate or mitigate the above-described disadvantages.
In accordance with the present invention, there is provided a method of semiconductor device fabrication comprising forming at least one indentation in a surface of a semiconductor body, partially filling the indentation with a filler material such that walls of the indentation are exposed above an upper surface of the filler material, and introducing and diffusing first and second dopants through the exposed walls of the indentation to form first and second doped regions, the first doped region extending into the semiconductor body around the filled portion of the indentation to a first region boundary which is at a predetermined first depth relative to the upper surface of the filler material, and the second doped region extending into the semiconductor body around the filled portion of the indentation to a second region boundary which is at a predetermined second depth relative to the upper surface of the filler material, the first and second depths being different such that a region of predetermined thickness is defined adjacent the indentation between the first and second boundaries.
Preferably, the indentations are elongate trenches, and may have U-shaped cross-section.
The step of partially filling the indentations with a filler material may comprise filling completely the indentations with filler material, then etching the filler material part way into the indentations.
Preferably, the filler material is polysilicon.
Preferably, a layer of dielectric is formed upon surfaces of the trench prior to the trench being partially filled. Dopant may be introduced into the side walls of the trench through this dielectric layer. Alternatively, the dielectric layer may be at least partially removed from those surfaces of the trench which are exposed above the partially filled portion of the trench, prior to the introduction of dopant.
Preferably, at least a portion of the trench masking layer is retained on the said surface of the semiconductor body and functions as a barrier to introduction of at least one of the dopants.
Preferably, at least one of the dopants is produced by an ionic source which is disposed at an angle to the trench.
In one embodiment, the first dopant is arranged to penetrate further into the side walls of the trench than the second dopant, and the second dopant is prevented from entering at least part of the first surface of the semiconductor by means of an at least partially retained trench masking layer on the first surface. The thickness and composition of the trench masking layer may be chosen such that it functions as an effective barrier to an implant of the second dopant carried out at low energy, but is a relatively poor barrier to an implant of the first dopant carried out at high energy. Preferably in this embodiment, the semiconductor device is a MOSFET with gate electrode regions provided by the filler material, and body and source regions provided by the first and second doped regions.
In an alternative embodiment the choice of dopant species and diffusion conditions is such that the second dopant penetrates further than the first, the first dopant providing the MOSFET source region and the second dopant the MOSFET body region. In this case, the masking layer used to define the trench etch is at least partially retained at the stage of first (source) dopant introduction, but may be partially or wholly removed prior to introduction of the second (body) dopant, enhancing the degree to which body dopant enters the substrate via the first surface.
In any embodiment the MOSFET may be a n-p-n (n-channel type) or a p-n-p (p-channel type) structure.
The semiconductor body may be formed on a further body of semiconductor which defines a drain region. A further layer of opposite conductivity type to the further body of semiconductor may be formed on the side of the further body of semiconductor remote from the said surface of the semiconductor body.